View M69KM096AACW8_3868679.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. july 2006 rev 2 1/59 1 m69km096aa 64 mbit (4 mb x16), 83mhz clock rate, 1.8v supply, multiplexed i/o, bare die, burst psram feature summary supply voltage ?v cc = 1.7 to 1.95v core supply voltage ?v ccq = 1.7 to v cc for i/o buffers multiplexed addr ess/data bus asynchronous operating modes ? random read: 70ns access time ? asynchronous write synchronous modes ? synchronous read: fixed length (4-, 8-, 16-, and 32-word) or continuous burst clock frequency: 83mhz (max) ? synchronous write: continuous burst low power consumption ? active current: < 25ma ? standby current: 140a ? deep power-down current: < 10a low power features ? partial array self-refresh (pasr) ? deep power-down (dpd) mode ? automatic temperature-compensated self- refresh operating temperature ? ?30c to +85c the m69km096aa is only available as part of a multi-chip package product. wafer www.st.com
contents m69km096aa 2/59 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 address inputs (a16-a21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 address inputs or data input/outputs (adq0-adq15) . . . . . . . . . . . . . . . 9 2.3 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 output enable (g) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 upper byte enable (ub) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 lower byte enable (lb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 clock input (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 configuration register enable (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 latch enable (l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.12 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 v ccq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 partial array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 automatic temperature compensated self refresh . . . . . . . . . . . . . . . . 13 5 standard asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . 14 5.1 asynchronous read and write modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 configuration registers asynchronous read and write . . . . . . . . . . . . . 14 6 synchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
m69km096aa contents 3/59 6.1 nor-flash synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 full synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 synchronous burst read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.1 variable latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.2 fixed latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 row boundary crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.4 synchronous burst read interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 synchronous burst write interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 synchronous burst read and write suspend . . . . . . . . . . . . . . . . . . . . . 19 7 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 programming and reading registers using the cr controlled method . . 24 7.1.1 read configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.2 program configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 programming and reading the registers using the software method . . . 25 7.3 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.1 operating mode bit (bcr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.2 latency type (bcr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.3 latency counter bits (bcr13-bcr11) . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.4 wait polarity bit (bcr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.5 wait configuration bit (bcr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.6 driver strength bits (bcr5-bcr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.7 burst wrap bit (bcr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.8 burst length bits (bcr2-bcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4.1 deep power-down bit (rcr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4.2 partial array refresh bits (rcr2-rcr0) . . . . . . . . . . . . . . . . . . . . . . . 32 7.5 device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
list of tables m69km096aa 4/59 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. standard asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. asynchronous write operations (nor-flash synchronous mode) . . . . . . . . . . . . . . . . . . 19 table 4. synchronous read operations (nor-flash synchronous mode) . . . . . . . . . . . . . . . . . . . 20 table 5. full synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. register selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. bus configuration register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. variable latency counter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10. fixed latency counter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 11. refresh configuration register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. device id register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. asynchronous write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 19. clock related ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 20. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 21. synchronous burst write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 22. power-up and deep power-down ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 23. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
m69km096aa list of figures 5/59 list of figures figure 1. logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. variable latency mode , no refresh collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4. fixed latency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5. refresh collision during synchronous burst read in variable latency mode . . . . . . . . . . 23 figure 6. set configuration register (software method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. read configuration register (software method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 9. wait polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 10. ac measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11. ac input transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13. asynchronous random read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 14. cr controlled configuration register read followed by read, asynchronous mode . . . 39 figure 15. asynchronous write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 16. asynchronous write followed by read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 17. cr controlled configuration register program, asynchronous mode . . . . . . . . . . . . . . . . 43 figure 18. clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 19. 4-word synchronous burst read ac waveforms (variable latency mode). . . . . . . . . . . . 46 figure 20. synchronous burst read suspend and resume ac waveforms . . . . . . . . . . . . . . . . . . . . 47 figure 21. burst read showing end-of-row condition ac waveforms (no wrap) . . . . . . . . . . . . . . . 48 figure 22. cr controlled configuration register read followed by read, synchronous mode . . . . 49 figure 23. 4-word synchronous burst write ac waveforms (variable latency mode) . . . . . . . . . . . 51 figure 24. burst write showing end-of-row condition ac waveforms (no wrap) . . . . . . . . . . . . . . . 52 figure 25. synchronous burst write followed by read ac waveforms (4 words) . . . . . . . . . . . . . . . 53 figure 26. cr controlled configuration register program, synchronous mode. . . . . . . . . . . . . . . . . 54 figure 27. power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 28. deep power-down entry and exit ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
summary description m69km096aa 6/59 1 summary description the m69km096aa is a 64 mbit (67,108,864 bit) psram, organized as 4,194,304 words by 16 bits. it uses a high-speed cmos dram technology implemented using a one transistor- per-cell topology that achieves bigger array sizes. it provides a high-density solution for low- power handheld applications. the device operates from a 1.7 to 1.95v supply voltage. it has a 16-bit data bus. to reduce the number of pins. the first sixteen address lines are multiplexed with the data input/output signals on the multiplexed address/data bus adq0-adq15. the remaining address lines a16-a21 are the msb addresses. the psram interface supports various operating modes: asynchronous random read and write - when operating in one of these modes, the m69km096aa is compatible with low power srams. synchronous modes that increase read and write speeds. two types of synchronous modes are available: ? flash-nor: the device operates in synchronous mode for read operations and asynchronous mode for write operations. ? full synchronous: the device supports synchronous transfers for both read and write operations. the m69km096aa features three registers: the bus configuration register (bcr) and the refresh configuration register (rcr): user-programmable configuration registers, which are used to define the device operation. a read-only device id register (didr) containing device identification information. the bus configuration register (bcr) indicate s how the device interacts with the system memory bus. the refresh configuration register (rcr) is used to control how the memory array refresh is performed. at power-up, these registers are automatically loaded with default settings and can be updated any time during normal operation. psrams are based on the dram technology, but have a transparent internal self-refresh mechanism that requires no additional support from the system memory microcontroller. to minimize the value of the standby current during self-refresh operations, the m69km096aa includes three system-accessible mechanisms configured via the refresh configuration register (rcr): partial array self refresh (pasr) performs a limited refresh of the part of the psram array that contains essential data. deep power-down (dpd) mode completely halts the refresh operation. it is used when no essential data is being held in the device. automatic temperature compensated self refresh (tcsr) adjusts the refresh rate according to the operating temperature.
m69km096aa summary description 7/59 figure 1. logic diagram table 1. signal names a16-a21 address inputs adq0-adq15 address inputs or data input/outputs e chip enable input cr configuration register enable input g output enable input w write enable input ub upper byte enable input lb lower byte enable input k clock input l latch enable input wait wait output v cc core supply voltage v ccq input/output buffers supply voltage v ss ground v ssq input/output buffers ground ai11583 6 a16-a21 w addq0-dq15 v cc m69km096aa g 16 e ub lb v ss cr k l v ccq v ssq wait
summary description m69km096aa 8/59 figure 2. functional block diagram 1. this functional bloc k diagram illustrates si mplified device operation. ai11584 k wait control logic cr l ub lb w e g bus configuration register (bcr) bus configuration register (bcr) device id register (didr) refresh configuration register (rcr) a16-a21 address decoder i/o mux and buffers 4,096k x 16 memory array adq0- adq15
m69km096aa signal descriptions 9/59 2 signal descriptions the signals are summarized in figure 1: logic diagram , and table 1: signal names . 2.1 address inputs (a16-a21) the address inputs a16-a21 are used in conjunction with adq0 to adq15, to select the cells in the memory array that are accessed during read and write operations. 2.2 address inputs or data input/outputs (adq0-adq15) adq0-adq15 support multiplexed address/data sequencing. they are used to input addresses to the memory array, or to program data in the memory array. addresses are internally latched during read and write operations. adqo-adq15 are also used to define the value to be loaded into the bcr or the rcr, along with a16- a21 address inputs. 2.3 chip enable (e ) chip enable, e , activates the device when driven low (asserted). when de-asserted (v ih ), the device is disabled and goes automatically in low-power standby mode or deep power- down mode, accordin g to the rcr settings. 2.4 output enable (g ) when held low, v il , the output enable, g , enables the bus read operations of the memory. 2.5 write enable (w ) write enable, w , controls the bus write operation of the memory. when asserted (v il ), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array. 2.6 upper byte enable (ub ) the upper byte enable, ub , gates the data on the upper byte of the address inputs/ data inputs/outputs (adq8-adq15) to or from the upper part of the selected address during a write or read operation.
signal descriptions m69km096aa 10/59 2.7 lower byte enable (lb ) the lower byte enable, lb , gates the data on the lower byte of the address inputs/data input/outputs (adq0-adq7) to or from the lower part of the selected address during a write or read operation. if both lb and ub are disabled (high), the device will di sable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as e remains low. 2.8 clock input (k) the clock, k, is an input signal to synchronize the memory to the microcontroller or system bus frequency during synchronous burst read and write operations. the clock input signal increments the device internal address counter. the addresses are latched on the rising edge of the clock k, when l is low during synchronous bus operations. latency counts are defined from the first clock rising edge after l falling edge to the first data input latched or the first data output valid. the clock input is required during all synchronous operations and must be kept low during asynchronous operations. 2.9 configuration register enable (cr) when this signal is driven high, v ih , bus read or write operations access either the value of the refresh configuration register (rcr) or the bus configuration register (bcr) according to the value of a19. 2.10 latch enable (l ) in synchronous mode, addresses are latched on the rising edge of the clock k when the latch enable input, l is low. in asynchronous mode, addresses are latched on l rising edge. 2.11 wait (wait) the wait output signal provides data-valid feedback during synchronous burst read and write operations. the signal is gated by e . driving e high while wait is asserted may cause data corruption. once a read or write operation has been initiated, the wait signal goes active to indicate that the m69km096aa device requires additional time before data can be transferred. the wait signal also is used for arbitration when a read or write operation is launched while an on-chip refresh is in progress (see figure 5: refresh collis ion during sy nchronous burst read in variable latency mode ). typically, the wait pin of the m69km096aa can be connected to a shared wait signal used by the processor to coordinate transactions with multiple memories on the synchronous bus. see section 3: power-up for details on the wait signal operation.
m69km096aa signal descriptions 11/59 2.12 v cc supply voltage the v cc supply voltage is the core supply voltage. 2.13 v ccq supply voltage v ccq provides the power supply for the i/o pins. this allows all outputs to be powered independently from the core power supply, v cc . 2.14 v ss ground. the v ss ground is the reference for all voltage measurements. 2.15 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ccq . v ssq must be connected to v ss .
power-up m69km096aa 12/59 3 power-up to guarantee correct operation, a specific power-up sequence must be followed to initialize the m69km096aa. power must be applied simultaneously to v cc and v ccq . once v cc and v ccq have reached a stable level (see figure 28: deep power-down entry and exit ac waveforms and figure 27: power-up ac waveforms ), the device will require t vchel to complete its self-initializ ation process. during the initialization period, the e signal must remain high. once initialization has completed, the device is ready for normal operation. initialization will load the bus configuration re gister (bcr) and the refresh configuration register (rcr) with their default settings (see table 7: bus configuration register definition , and table 11: refresh configuration register definition ). 4 low-power modes 4.1 standby when the device is in standby, the current consumption is reduced to the level necessary to perform the memory array refres h operation. the device will en ter standby when a read or write operation is completed, depending on the operating mode (asynchronous, synchronous). for details on how to enter standby, refer to table 2: standard asynchronous operating modes , table 3: asynchronous write operations (nor-flash synchronous mode) and table 4: synchronous read operatio ns (nor-flash synchronous mode) . 4.2 deep power-down deep power-down (dpd) is used by the system memory microcontro ller to disable the psram device when its storage capabilities are not needed. all refresh operations are then disabled. for the device to enter deep power-down mode, bit 4 of the rcr must be set to ?0? and chip enable, e , must go high, v ih . when the deep power-down is enabled, the data stored in the device may be corrupted and the bcr, the rcr and didr contents are saved. the device exits from deep power-down mode when the chip enable signal, e , has been low again for a minimum time of t eleh(dp) (see table 22: power-up and deep power-down ac characteristics and figure 27: power-up ac waveforms ). bit 4 of the rcr will be automatically set to ?1?. once the deep power-down is exited, the device will be available for normal operations after t vchel (time to perform an initialization sequence) during this delay, the current consum ption will be higher than the specified standby levels, but considerably lower than the active current. the content of the registers will be restored after deep power-down. for details on how to enter deep power-down, refer to table 2: standard asynchronous operating modes , table 3: asynchronous write operations (nor-flash synchronous mode) and table 4: synchronous read operations (nor-flash synchronous mode) .
m69km096aa low-power modes 13/59 4.3 partial array self refresh the partial array self refresh (pasr) performs a limited refresh of part of the psram array. this mechanism enables the device to reduce the standby current by refreshing only the part of the memory array that contains essential data. different refresh options can be defined by setting the rcr0 to rcr2 bits of the rcr: full array one eighth of the array one half of the array one quarter of the array none of the array these memory areas can be located either at the top or bottom of the memory array. the wait signal is used for arbitration when a read/write operation is launched while an on- chip refresh is in progress. if locations are addressed while they are undergoing refresh, the wait signal will be asserted for additional cl ock cycles, until the refresh has completed (see figure 5: refresh collision during synchro nous burst read in variable latency mode ). when the refresh operation is completed, the re ad or write operation will be allowed to continue normally. 4.4 automatic temperature compensated self refresh the leakage current of dram capacitive storage elements increases with the temperature. at lower temperatures, the refresh rate can be decreased to minimize the standby current. the m69km096aa is based on dram architecture, consequently it requires increasingly frequent refresh operations to maintain data integrity as the temperature increases. the automatic temperature compensated self refresh mechanism (tcsr) that the devices feature, automatically adjusts the refresh rate depending on the operating temperature.
standard asynchronous operating modes m69km096aa 14/59 5 standard asynchronous operating modes the m69km096aa supports asynchronous read and write modes (random read, asynchronous write). the device is put in asynchronous mode by setting bit 15 (bcr15) of the bcr to ?1?. during asynchronous operations, the wait signal should be ignored and the clock input signal k should be held low, v il . refer to table 2: standard asynchronous operating modes for a detailed description of asynchronous operating modes. 5.1 asynchronous read and write modes at power-up, the device defaults to asynchronous random read mode (bit bcr15 set to ?1?). this mode uses the industry standard control bus (e , g , w , lb , ub ). read operations are initiated by bringing e , g and l low, v il , while keeping w high, v ih , and driving the address onto the multiplexed address/data bus. l is then taken high, v ih , to capture the address, and g is taken low, v il . valid data will be gated through the output buffers after the specific access time t elqv has elapsed. write operations occur when e , w and l are driven low, v il with the address on the multiplexed address/data bus. l is then taken high, v ih , to capture the address, and the write data is driven onto the bus. during asynchronous random write operations, the g signal is ?don't care? and w will override g . the data to be written is latched on the rising edge of e , w , lb or ub (whichever occurs first). the write operation is terminated by de- asserting e , w , lb or ub . see figure 13 , and ta b l e 1 7 for details on asynchronous read ac waveforms and characteristics and figure 15 , and ta b l e 1 8 for details of asynchronous write ac waveforms and characteristics. 5.2 configuration registers as ynchronous read and write programming the registers (bcr and rcr) an d reading the register s (bcr, rcr or didr) can be performed using the cr controlled method in standard asynchronous mode.
m69km096aa standard asynchronous operating modes 15/59 table 2. standard asynchronous operating modes (1) asynchronous modes power e l w g ub lb cr a19 a18 a16, a17, a20, a21 adq0- adq7 adq8- adq15 word read active (i cc ) v il \_/ v ih v il v il v il v il address in valid address in/ data out valid lower byte read v il v ih v il v il address in valid address in/ data out valid high-z upper byte read v il v il v ih v il address in valid high-z address in/ data out valid word write v il v ih v il v il v il address in valid address in/ data in valid lower byte write v ih v il v il address in valid address in/ data in valid data in invalid upper byte write v il v ih v il address invalid data in invalid address in/ data in valid read configuration register (cr controlled method) v ih v il v il v il v ih 00(rcr) 10(bcr) x1(didr) x address in/ bcr, rcr or didr content valid program configuration register (cr controlled) (2) v il v il v ih xx 00(rcr) 10(bcr) (3) bcr/ rcr data address in valid output disable/no operation active (i cc ) x v ih xx xv il x x x high-z deep power-down (4) deep power- down (i ccpd) v ih x x x x x x x x high-z standby standby (i pasr ) v ih xxxx xv il x x high-z 1. the clock signal, k, must remain low in asynchronous operating mode. 2. bcr and rcr only. 3. a18 and a19 are used to select the bcr, the rcr or the didr. 4. the device enters deep power-down mode by driving the chip enable signal, e , from low to high, with bit 4 of the rcr set to ?0?. the device remains in deep power-down mode until e goes low again and is held low for t eleh(dp) .
synchronous operating modes m69km096aa 16/59 6 synchronous operating modes the synchronous modes allow high-speed read and write operations synchronized with the clock. the m69km096aa supports two types of synchronous modes: nor-flash :- this mode greatly simplifies the interfacing with traditional burst-mode flash memory microcontrollers. full synchronous : both read and write are performed in synchronous mode. all the options related to the synchronous modes can be configured through the bus configuration register, bcr. in particular, t he device is put in synchronous mode, either nor-flash or full synchronous, by setting bit bcr15 of the bus configuration register to ?0?. the device will automatically detect whether the nor-flash or the full synchronous mode is being used by monitoring the clock, k, and the latch enable, l , signals. if a rising edge of the clock k is detected while l is held low, v il (active), the device operates in full synchronous mode. 6.1 nor-flash synchronous mode in this mode, the device operates in synchronous mode for read operations, and in asynchronous mode for write operations. asynchronous write operations are performed at word level, with lb and ub low. the data is latched on e , w , lb , ub , whichever occurs first. rcr and bcr registers can be programmed in nor-flash asynchronous write mode, using the cr controlled method (see section 7.1: programming a nd reading registers using the cr controlled method ). a program configuration register operation can only be issued if the device is in idle state and no burst operations are in progress. no r-flash asynchronous write operations are described in table 3: asynchronous write operations (nor-flash synchronous mode) . synchronous read operations are also performed at word level. they are controlled by the state of e , l , g , w , lb and ub signals when a rising edge of the clock signal, k, occurs. the initial burst read access latches the burst start address. the number of words to be output is controlled by bits 0 to 2 of the bcr. the first data will be output after a nu mber of clock cycles, also called latency. nor-flash synchronous burst read operations are described in table 4: synchronous read operations (nor-flash synchronous mode) . when a burst write operation is initiated or when switching from nor-flash mode to full synchronous mode, the delay from e low to clock high, t elkh , should not exceed 20ns. however, when it is not possible to meet these specifications, special care must be taken to keep addresses stable after driving the write enable signal, w , low. write operations are considered as asynchronous operations until the device detects a valid clock edge and hence the address setup time of t avwl must be satisfied (see figure 5: refresh collision during sy nchronous burst read in variable latency mode ).
m69km096aa synchronous operating modes 17/59 6.2 full synchronous mode in full synchronous mode, the device performs read and write operations synchronously. synchronous read and write operations are performed at word level. the initial burst read and write access latches the burst start address. the number of words to be output or input during synchronous read and write operations is controlled by bits 0 to 2 of the bcr. during burst read and write oper ations, the first data will be output after a number of clock cycles defined by the latency value. programming the registers (bcr and rcr) an d reading the register s (bcr, rcr or didr) can be performed using the cr controlled method in full synchronous mode. full synchronous operations are described in table 5: full synchronous mode . 6.3 synchronous burst read and write during synchronous burst read or write operations, addresses are latched on the rising edge of the clock k when l is low and data are latched on the rising edge of k. the write enable, w , signal indicates whether the operation is going to be a read (w =v ih ) or a write (w =v il ). the wait output will be asserted as soon as a synchronous burst operation is initiated and will be de-asserted to indicate when data are to be transferred to (or from) the memory array. the burst length is the number of words to be output or input during a synchronous burst read or write operation. it can be configured as 4, 8, 16 or 32 words or continuous through bit bcr0 to bcr2 or the burst configuration register. the latency defines the number of clock cycles between the beginning of a burst read operation and the first data output (counting from the first clock edge where l was detected low) or between the beginning of a burst write operation and the first data input. the latency can be set through bits bcr13 to bcr11 of the bus configuration register. the latency can also be configured to fixed or variable by programming bit bcr14. by default, the latency type is set to variable. synchronous read operations are performed in both fixed and variable latency mode while synchronous write operations are only performed with fixed latency. see figure 19 , figure 21 , and figure 24 , figure 25 , for details on synchronous read and write ac waveforms, respectively. 6.3.1 variable latency in variable latency mode, the latency programmed in the bcr is not guaranteed and is maintained only if there is no conflict with a refresh operation. the latency set in the bcr is applicable only for an initia l burst read access, when no refresh request is pending. for a given latency value, the variable latency mode allows higher operating frequencies than the fixed latency mode (see table 9: variable latency counter configuration and figure 3: variable latency mode , no refresh collision ). burst write operations are always performed at fixed latency, even if bcr14 is configured to variable latency (see section 6.3.2: fixed latency ). monitoring of the wait signal is recommended for reliable operation in this mode. see figure 19 . and figure 25 for details on synchronous burst read and write ac waveforms in variable latency mode.
synchronous operating modes m69km096aa 18/59 6.3.2 fixed latency the latency programmed in the bcr is the re al latency. the number of clock cycles is calculated by taking into account the time necessary for a refresh operation and the time necessary for an initial burst access. this limits the operating frequency for a given latency value (see table 10: fixed latency counter configuration and figure 4: fixed latency mode ). it is recommended to use the fixed latency mode if the microcontroller cannot monitor the wait signal. 6.3.3 row boundary crossing row boundary crossings between adjacent rows may occur during burst read and write operations. row boundary crossings are not handled automatically by the psram. the microcontroller must stop the burst operation at the row boundary and restart it at the beginning of the next row. burst operations must be stopped by driving the chip enable signal, e , high, after the wait signal falling edge. e must transition within the first clock cycle after the last valid data output is sampled by the rising edge of the clock k. refer to figure 21 and figure 24 for details on how to manage row boundary crossings during burst operations. 6.3.4 synchronous burst read interrupt ongoing burst read operations can be interrupted to start a new burst cycle by either of the following means: driving e high, v ih , and then low, v il on the next clock cycle (recommended). if necessary, refresh cycles will be added during the new burst operation to schedule any outstanding refresh. if variable latency mode is set, additional wait cycles will be added if a refresh operation is scheduled during the synchronous burst read interrupt. wait monitoring is mandatory for proper system operation. starting a new synchronous burst read operation without toggling e . an ongoing burst read operation can be interrupted only after the first valid data is output. when a new burst access starts, i/o signals immediately become high impedance. 6.4 synchronous burst write interrupt ongoing burst write operations can be interrupted to start a new burst cycle by either of the following means: driving e high, v ih , and then low, v il on the next clock cycle (recommended), starting a new synchronous burst write without toggling e . considering that burst writes are always performed in fixed latency mode, refresh is never scheduled. a maximum chip enable, e , low time (t eleh ) must be respected for proper device operation. an ongoing burst write can be interrupted only after the first data is input. when a new burst access starts, i/o signals immediately become high impedance.
m69km096aa synchronous operating modes 19/59 6.5 synchronous burst read and write suspend synchronous burst read and write operations can be suspended by halting the clock k holding it low, v il . the status of the i/o signals will depend on the st atus of output enable input, g . the device internal address counter is suspended and data outputs become high impedance t ghqz after the rising edge of the output enable signal, g . it is prohibited to suspend the first data output at the beginning of a synchronous burst read. see figure 20 for details on the synchronous burst read and write suspend mechanisms. during synchronous burst read and synchronous burst write suspend operations, the wait output will be asserted. bit bcr8 of th e bus configuration register is used to configure when the transition of the wait output signal between the asserted and the de- asserted state occurs with respect to valid data available on the data bus. table 3. asynchronous write operations (nor-flash synchronous mode) asynchronous operations power k (1) e l w g ub , lb cr a19 a18 a16, a17, a20, a21 adq0- adq15 word write (2) active (i cc ) v il v il v il v il v ih v il v il address in valid address in/data in valid program configuration register (cr controlled) (3) v il v il v il xxv ih 00(rcr) 10(bcr) rcr/bc r data x output disable/ no operation (2)(4) active (i cc )v il xxxxx v il high-z standby (5)(4) standby (i pasr )v ih xxx xv il x high-z deep power-down (6) deep power- down (i ccpd) v ih xxxxx x high-z 1. k must be held low during asynchronous read and write operat ions. it must also be kept low for the device to consume standby current during standby and deep power-do wn modes, and during burst suspend operations. 2. the device will consume active power in this mode whenever addresses are changed. 3. bcr and rcr only. 4. v in = 0v or v ccq ; all signals must be stable in order to achieve standby current. 5. when the device is in standby mode, address inputs and dat a inputs/outputs are internally isolated from any external influence. 6. the device enters deep power-down mode by driving the chip enable signal, e , from low to high, with bit 4 of the rcr set to ?0?. the device remains in deep power-down mode until e goes low again and is held low for t eleh(dp) .
synchronous operating modes m69km096aa 20/59 ) table 4. synchronous read operations (nor-flash synchronous mode) synchronous operations power k (1) e l w g lb , ub wait (2) cr a19 a18 a16, a17, a20, a21 adq15- adq0 initial burst read (3)(4) active (i cc ) v il v il v ih v ih v il low-z v il address in valid x subsequent burst read (3)(4)(5) v il v ih xxv il v il x address in/data out valid read configuration register (cr controlled method) (3)(6) v il v il v ih v il v il v ih 00(rcr) 10(bcr) x1(didr) x address in/ bcr, rcr or didr content valid output disable/no operation (4)(7) active (i cc ) v il xxx x v il x high-z standby (7)(8) standby (i pa s r ) v il v ih xxx x high-z v il x high-z deep power- down (9) deep power- down (i ccpd) v il v ih x x x x x x high-z 1. k must be held low for the device to consume standby current during standby and deep power-down modes, and during burst suspend operations. 2. the wait polarity is confi gured through bit 10 (bcr10) of t he bus configuration register. 3. the burst mode is configured through bit 15 (bcr15) of the bus configuration register. 4. the device will consume active power in this mode whenever addresses are changed. 5. burst read interrupt and suspend are described in dedicated paragraph of the section 6: synchronous operating modes . 6. the configuration register is output during the initial burst read. the following read operations are similar to subsequent burst read operations. e must be held low for the equivalent of a single- word burst read (as indicated by the wait signal). 7. v in = 0v or v ccq ; all signals must be stable in order to achieve standby current. 8. when the device is in standby mode, address inputs and dat a inputs/outputs are internally isolated from any external influence. 9. the device enters deep power-down mode by driving the chip enable signal, e , from low to high, with bit 4 of the rcr set to ?0?. the device remains in deep power-down mode until e goes low again and is held low for t eleh(dp) .
m69km096aa synchronous operating modes 21/59 table 5. full synchronous mode synchronous mode power k (1) e l w g lb , ub wait (2) cr a19 a18 a16, a17, a20, a21 adq15- adq0 initial burst read (3)(6) active (i cc ) v il v il v ih v ih v il low-z v il address in valid x subsequent burst read (3)(4)(6) v il v ih xxv il xx address in/data out valid initial burst write (3)(6) v il v il v il v ih x address in valid address in/data in valid subsequent burst write (3)(6) v il v ih xv ih v il xx x address in/data in valid program configuration register (cr controlled) (3)(5) v il v il v il v ih xv ih 00(rcr) 10(bcr) rcr/bcr data x read configuration register (cr controlled method) (3)(5) v il v il v ih v il v il v ih 00(rcr) 10(bcr) x1(didr) x address in/ bcr, rcr or didr content valid no operation (6)(8) active (i cc ) v il xv ih v ih xv il x high-z standby (7)(8) standby (i pasr ) v il v ih xxx x high-z v il x high-z deep power- down (9) deep power- down (i ccpd) v il v ih x x x x x x high-z 1. k must be held low for the device to consume standby current during standby and deep power-down modes, and during burst suspend operations. 2. the wait polarity is confi gured through bit 10 (bcr10) of t he bus configuration register. 3. the burst mode is configured through bit 15 (bcr15) of the bus configuration register. 4. burst read interrupt, suspend, terminate and burst writ e interrupt, suspend and terminat e are described in dedicated paragraph of the section 6: synchronous operating modes . 5. the configuration register is output during the initial burst operation (read or write). the following read or write operatio ns are similar to subsequent burst operations. e must be held low for the equivalent of a single-word burst operation (as indicated by the wait signal). 6. the device will consume ac tive power in this mode whenever addresses are changed. 7. when the device is in standby mode, address inputs and dat a inputs/outputs are internally isolated from any external influence. 8. v in = 0v or v ccq ; all signals must be stable in order to achieve standby current. 9. the device enters deep power-down mode by driving the chip enable signal, e , from low to high, with bit 4 of the rcr set to ?0?. the device remains in deep power-down mode until e goes low again and is held low for t eleh(dp) .
synchronous operating modes m69km096aa 22/59 figure 3. variable latency mode, no refresh collision figure 4. fixed latency mode 1. see table 20: synchronous burst read ac characteristics for details on the synchronous r ead ac characteristics shown in the above waveforms. a16-a21 adq0-adq15 k address valid q 1 hi z 012345 q 4 q 3 q 2 latency = 3 clock cycles ai11585 l hi z q 1 q 3 q 2 q 5 q 4 67 latency = 4 clock cycles adq0-adq15 address valid address valid a16-a21 adq0-adq15 out k address valid q 1 hi z n-1 cycle n cycle q 4 q 3 q 2 tavqv ai11586 q 5 tllqv e telqv tkhqv2 l address valid
m69km096aa synchronous operating modes 23/59 figure 5. refresh collision during synchronous burst read in variable latency mode 1. additional wait states are in serted to allow refresh completion. the latency is set to 3 clo ck cycles (bcr13-bcr11 = 010). the wait must be active low, v il , (bcr10 = 0) and asserted during delay (bcr8= 0). a16-a21 wait adq0-adq15 k additional wait states inserted to allow refresh completion address valid ai11587 l e g w hi z hi z lb/ub q0 q1 q2 q3 address valid
configuration registers m69km096aa 24/59 7 configuration registers the m69km096aa features three registers: the bus configuration register (bcr) the refresh configuration register (rcr) the device id register (didr) bcr and rcr are user-programmable registers that define the device operating mode. they are automatically loaded with default settings during power-up, and selected by address bits a18 and a19 (see table 6: register selection ). the didr is a read-only register that contains information about the device identification. it is selected by setting address bit a18 to ?1? with a19 ?don?t care?. the configuration registers can be programmed and read using two methods: the cr controlled method (or hardware method) the software method 7.1 programming and reading registers using the cr controlled method 7.1.1 read confi guration register the content of a register is read by issuing a read operation with configuration register enable signal, cr, high, v ih . address bits a18 and a19 select the register to be read (see table 6: register selection ). the value contained in the register is then available on data bits dq0 to dq15. the bcr, the rcr and th e didr can be read either in normal asynchronous or synchronous mode. the cr pin has to be driven high prior to any access. see ta bl e 4 and ta bl e 5 for a detailed description of configuration register read by the cr controlled methods and figure 14 and figure 22 , cr controlled configuration register read waveforms in asynchronous and synchronous mode. 7.1.2 program conf iguration register bcr and rcr registers can be programmed by issuing a bus write operation, in asynchronous or synchronous mode (nor-flash or full synchronous), with configuration register enable signal, cr, high, v ih . address bits a18 and a19 allow to select between bcr and rcr (see table 6: register selection ). in synchronous mode, the values placed on address lines a0 to a15 are latched on the rising edge of l , e , or w , whichever occurs first. in asynchronous mode, a register is programmed by toggling l signal. lb and ub are ?don?t care?. the cr pin has to be driven high prior to any access. refer to ta b l e 3 and ta bl e 5 for a detailed description of configuration register program by the cr controlled method and to figure 17 and figure 26 , showing cr controlled configuration register program waveforms in asynchronous and synchronous mode.
m69km096aa configuration registers 25/59 7.2 programming and reading the registers using the software method all registers (bcr, rcr, didr) can be read by issuing a read configuration register sequence (see figure 7: read configuration register (software method) . bcr and rcr can be programmed by issuing a set configuration register sequence (see figure 6: set configuration register (software method) . the timings will be identical to those described in table 17: asynchronous read ac characteristics . the configuration register enable input, cr, is ?don?t care?. read configuration register and set configuration register sequences both require 4 read and write cycles. these cycles are performed in asynchronous mode, whatever the device operating mode: 2 bus read and one bus write cycles to a unique address location, 7fffffh, indicate that the next operation will read or write to a configuration regist er. the data written during the third cycle must be ?0000h? to access the rcr, ?0001h? to access the bcr, and ?0002h? to access the didr during the next cycle. the fourth cycle reads from or writes to the configuration register. the timings for programming and reading the registers by the software method are identical to the asynchronous write and read timings. table 6. register selection register read or write operation a18 a19 rcr read/write 0 0 bcr read/write 0 1 didr read-only 1 x
configuration registers m69km096aa 26/59 figure 6. set configuration register (software method) 1. only the bus configuration register (bcr) and the refresh configuration regi ster (rcr) can be modified. 2. to program the bcr or the rcr on last bus write cycl e, dq0-dq15 must be set to ?0001h? and ?0000? respectively. 3. the highest order address location is not modified during this operation. 4. the control signals e , g , w , lb and ub , must be toggled as shown in the above figure. figure 7. read configuration register (software method) 1. to read the bcr, the rcr or the didr, on last bus read cyc le, dq0-dq15 must be set to ? 0001h? and ?0000?, respectively. 2. the highest order address location is not modified during this operation. 3. the control signals e , g , w , lb and ub , must be toggled as shown in the above figure. 7fffffh a16-a21 7fffffh g w e lb, ub ai11588 7fffffh 7fffffh 7fffffh adq0-adq15 (2) configuration register data t ehel2 t ehel2 t ehel2 read cycle read cycle write cycle write cycle l a16-a21 7fffffh e g w lb, ub ai11589 7fffffh 7fffffh 7fffffh adq0-adq15 (1) configuration register data tehel2 tehel2 tehel2 7fffffh read cycle read cycle write cycle read cycle l
m69km096aa configuration registers 27/59 7.3 bus configuration register the bus configuration register (bcr) defines how the psram interacts with the system memory bus. all the device operating modes are configured through the bcr. refer to ta bl e 7 for the description of the bus configuration register bits. 7.3.1 operating mode bit (bcr15) the operating mode bit allows the synchronous mode or the asynchronous mode (default setting) to be selected. selecting the synchr onous mode will allow the device to operate either in nor flash mode or in full synchronous burst mode. the device will automatically dete ct that the nor flash mode is being used by monitoring a rising edge of the clock signal, k, when l is low. if this should not be the case, the device operates in full synchronous mode. 7.3.2 latency type (bcr14) the latency type bit is used to configure the latency type. when the latency type bit is set to ?0?, the device operates in variable latency mode (only available for synchronous read mode). when it is ?1?, the fixed latency mode is selected and the latency is defined by the values of bits bcr13 to bcr11. refer to ta b l e 3 and ta bl e 4 for examples of fixed and variable latency configuration. 7.3.3 latency counter bits (bcr13-bcr11) the latency counter bits are used to set the number of clock cycles between the beginning of a read or write operation and the first data output or input. the latency counter bits can only assume the values shown in table 7: bus configuration register definition (see also figure 3 and figure 4 ). 7.3.4 wait polarity bit (bcr10) the wait polarity bit indicates whether the wait output signal is active high or low. as a consequence, it also determines whether the wait signal requires a pull-up or pull-down resistor to maintain the de-asserted state (see figure 9: wait polarity ). by default, the wait output signal is active high. 7.3.5 wait confi guration bit (bcr8) the system memory microcontroller uses the wait signal to control data transfer during synchronous burst read and write operations. the wait configuration bit is used to determine when the transition of the wait output signal between the asserted and the de-asserted state occurs with respect to valid data available on the data bus. when the wait configuration bit is set to ?0?, data is valid or invalid on the first clock rising edge immediately after the wait signal transition to the de-asserted or asserted state. when the wait configuration bit is set to ?1? (default settings ), the wait signal transition occurs one clock cycle prior to the data bus going valid or invalid. see figure 8: wait configuration example for an example of wait configuration.
configuration registers m69km096aa 28/59 7.3.6 driver strengt h bits (bcr5-bcr4) the driver strength bits allow to set the output drive strength to adjust to different data bus loading. normal driver strength (full drive) and reduced driver strength (half drive and a quarter drive) are available. by default, outputs are configured at ?half drive? strength. 7.3.7 burst wrap bit (bcr3) burst read operations can be confined inside the 4, 8, 16 or 32 word boundary (wrap mode). if the wrap mode is not enabled, the device outputs data sequentially up to the end of the row, regardless of burst boundaries. the burst wrap bit is used to select between ?wrap? and ?no wrap? mode. 7.3.8 burst length bits (bcr2-bcr0) the burst length bits set the number of words to be output or input during a synchronous burst read or write operation. they can be set for 4 words, 8 words, 16 words, 32 words or continuous burst (default settings), where all the words are output or input sequentially regardless of address boundaries (see also table 8: burst type definition ).
m69km096aa configuration registers 29/59 table 7. bus configuration register definition address bits bus configuration register bits name value description adq15 bcr15 operating mode bit 0 synchronous mode (nor flash or full synchronous mode) 1 asynchronous mode (default) adq14 bcr14 latency type 0 variable latency (default) 1 fixed latency adq13- adq11 bcr13- bcr11 latency counter bits 010 3 clock cycles 011 4 clock cycles (default) 100 5 clock cycles 101 6 clock cycles 110 7 clock cycles other configurations reserved (1) adq10 bcr10 wait polarity bit 0 wait active low 1 wait active high (default).see figure 9: wait polarity . adq9 - - must be set to ?0? reserved (1) adq8 bcr8 wait configuration bit 0 wait asserted during delay (see figure 8: wait configuration example ). 1 wait asserted one clock cycle before delay (default) adq7- adq6 - - must be set to ?0? reserved (1) adq5- adq4 bcr5-bcr4 driver strength bits 00 full drive 01 1/2 drive (default) 10 1/4 drive 11 reserved (1) adq3 bcr3 burst wrap bit 0 wrap (within the burst length) 1 no wrap (default) adq2- adq0 bcr2-bcr0 burst length bit 001 4 words 010 8 words 011 16 words 100 32 words 111 continuous burst (default) other configurations reserved (1) 1. programming the bcr with reserved value will forc e the device to use the default register settings.
configuration registers m69km096aa 30/59 table 8. burst type definition mode start add 4 words (sequential) bcr2-bcr0 = 001b 8 words (sequential) bcr2-bcr0=010b 16 words (sequential) bcr2- bcr0=011b 32 words (sequential) bcr2- bcr0=100b continuous burst bcr2-bcr0=111b wrap (bcr3=?0?) 0 0-1-2-3 0-1-2-3-4-5-6- 7 0-1-2-3-...-14-15 0-1-2-3- ...-30-31 0-1-2-3-..-511-. 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-...-14-15-0 1-2-3-...- 30-31-0 1-2-3-4-...-510-511- 2 2-3-0-1 2-3-4-5-6-7-0- 1 2-3-4-5-...-15-0-1 2-3- 4-...-31-0-1 2- 3-4-5-6-...-511- 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-...-15- 0-1-2 3-4-5-...-31-0-1-2 3-4-5-...-511- 4 4-5-6-7-0-1-2-3 4-5-...-15-0-1- 2-3 4-5-6-...-31-0- 1-2-3 4-5-...-511- 5 5-6-7-0-1-2-3-4 5-6-7-...-15-0-1-...- 4 5-6-7-..-31-0-1-..-4 5-6-7-...-511- 6 6-7-0-1-2-3-4-5 6-7-8-...-15-0-1-...- 5 6-7-8-...-31-0-1-...-5 6-7-8-...-511- 7 7-0-1-2-3-4-5-6 7-8-9-...15-0-1- ...-6 7-8-9-...-31-0-1-...-6 7-8-9-...-511- ... ... ... ... ... ... 14 14-15-0-1-2-...-13 14-15 -...-31-0-...-13 14-...511- 15 15-0-1-2-...-14 15-0-1- ...-31-0-...-14 15-...511- ... ... ... ... ... ... 30 30-31-0-...-28-29 30-...-511- 31 31-0-1-...-29-30 31-...-511- no wrap (bcr3=?1?) 0 0-1-2-3 0-1-2-3-4-5-6- 7 0-1-2-3-...-14-15 0-1-2-3- ...-30-31 0-1-2-3-..-511-. 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3- ..-15-16 1-2-3-4- ...-32 1-2-3-4-...-512- 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3- 4-...-17 2-3-4-...- 33 2-3-4-5-...-513- 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4- 5-...-18 3-4-5-...-34 3-4-5-...-514- 4 4-5-6-7-8-9-10-11 4-5-6-...- 19 4-5-6-...-35 4-5-6-...-515- 5 5-6-7-8-9-10-11-12 5-6-7- ...-20 5-6-7-...-36 5-6-7-...-516- 6 6-7-8-9-10-11-12-13 6-7-8-...- 21 6-7-8-...-37 6-7-8-...-517- 7 7-8-9-10-11-12-13-14 7-8-9-...- 22 7-8-9-...-38 7-8-9-...-518- ... ... ... 14 14-15-...-29 14-15-16-...-46 14-...-525- 15 15-16-17-...-30 15-16-17-...-47 15-...-526- ... ... ... 30 30-31-0-...-28-62 30-...-541- 31 31-0-1-...-29-63 31-...-542-
m69km096aa configuration registers 31/59 figure 8. wait configuration example figure 9. wait polarity table 9. variable latency counter configuration bcr13- bcr11 latency configuration code latency maximum clock rate normal refresh collision 010 2 (3 clocks cycles) 2 4 52 (19.2ns) 011 3 (4 clocks cycles) - default 3 6 83 (12ns) others reserved - - - table 10. fixed latency counter configuration bcr13- bcr11 latency configuration code latency maximum clock rate 010 2 (3 clocks cycles) 2 33 (30ns) 011 3 (4 clocks cycles)-default 3 52 (19.2ns) 100 4 (5 clocks cycles) 4 66 (15ns) 101 5 (6 clocks cycles) 5 75 (13.3ns) 110 6 (7 clocks cycles) 6 83 (12ns others reserved - - ai06795b dq0-dq15 bcr8='0', bcr10='1' data valid during current cycle k wait data[0] data[1] hi-z data[0] hi-z dq0-dq15 bcr8='1', bcr10='1' data valid during next cycle ai09963 dq0-dq15 k bcr8='0' bcr10='1' data[0] data[1] hi-z dq0-dq15 data[0] data[1] hi-z wait wait bcr8='0' bcr10='0'
configuration registers m69km096aa 32/59 7.4 refresh configuration register the role of the refresh configuration register (rcr) is: to define how the self refresh of the psram array is performed to select the deep power-down mode refer to ta b l e 1 1 for the description of the refresh configuration register bits. 7.4.1 deep power-down bit (rcr4) the deep power-down bit enables or disables all refresh-related operations. deep power- down mode is enabled when the rcr4 bit is set to ?0?, and remains enabled until this bit is set to ?1?. when e goes high, the device enters deep-power down mode and remains in this mode until the e mean time goes low and stays low for at least 10s. at power-up, the deep power-down mode is disabled. see the section 4.2: deep power-down for more details. 7.4.2 partial array re fresh bits ( rcr2-rcr0) the partial array refresh bits allow refresh operations to be restricted to a portion of the total psram array. the refresh options can be full array, one half, one quarter, one eighth or none of the array. these memory areas can be located either at the top or bottom of the memory array. by default, the full memory array is refreshed. table 11. refresh configuration register definition address bits refresh configuration register bits name value description adq15- adq5 - - must be set to ?0? reserved adq4 rcr4 deep power- down bit 0 deep power-down enabled 1 deep power-down disabled (default) adq3 - - must be set to ?0? reserved adq2- adq0 rcr2-rcr0 partial array refresh bits 000 full array refresh (default) 001 refresh of the bottom half of the array 010 refresh of the bottom quarter of the array 011 refresh of the bottom eighth of the array 100 none of the array 101 refresh of the top half of the array 110 refresh of the top quarter of the array 111 refresh of the top eighth of the array
m69km096aa configuration registers 33/59 7.5 device id register the device id register (didr) is a read-only register that contains the manufacturer code. it is preprogrammed by stmicroelectronics and cannot be modified by the user. refer to ta b l e 1 2 for the description of the bus configuration register bits. table 12. device id register definition address bits device id register bits name value description adq15 did15 row length 0 128 words 1 256 words adq14- adq11 didr14-didr11 design version 0000 a 0001 b 0010 c 0011 d 1111 p other configurations reserved adq10- adq8 didr10-didr8 device density 000 16 mbits 001 32 mbits 010 64 mbits 011 128 mbits 100 256 mbits other configurations reserved adq7- adq5 didr7-didr5 psram generation 001 1.0 010 1.5 011 2.0 other configurations reserved adq4- adq0 didr4-didr0 manufacturer id 00001 cypress 00010 infineon 00011 micron 00100 renesas 01111 stmicroelectronics other configurations reserved
maximum rating m69km096aa 34/59 8 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device relia bility. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality documents. table 13. absolute maximum ratings symbol parameter min max unit t a ambient operating temperature ?30 +85 c t stg storage temperature ?55 150 c v cc core supply voltage ?0.2 2.45 v v ccq input/output buffer su pply voltage ?0.2 2.45 v v io input or output voltage ?0.2 2.45 v
m69km096aa dc and ac parameters 35/59 9 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 14: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 10. ac measurement i/o waveform 1. logic states ?1? and ?0? correspond to ac test inputs driven at v ccq and v ss respectively. input timings begin at v ccq /2 and output timings end at v ccq /2. figure 11. ac input transitions table 14. operating and ac measurement conditions (1) 1. all voltages are referenced to v ss . parameter m69km096aa unit min max v cc supply voltage 1.7 1.95 v v ccq input/output buffer supply voltage 1.7 1.95 v load capacitance (c l )30pf output circuit protection resistance (r) 50 ? input pulse voltages (2)(3) 2. referenced to v ss . 3. v cc =v ccq 0v cc v input and output timing ref. voltages (2)(3) v cc /2 v input rise time t r and fall time t f (2)(3) 1v/ns ai09484c v ccq i/o timing reference voltage v ssq v ccq /2 90% 10% 90% 10% v cc typ v ss t r t f ai10122
dc and ac parameters m69km096aa 36/59 figure 12. ac measurement load circuit ai11289 v ccq /2 out device under test c l r table 15. capacitance symbol parameter test condition min max unit c in input capacitance t a = 25c, f = 1mhz, v in = 0v 26pf c io data input/output capacitance 3.5 6 pf table 16. dc characteristics symbol parameter refreshed array test conditions min. typ max. unit v oh (1) output high voltage i oh = ?0.2ma 0.8v ccq v v ol (1) output low voltage i ol = 0.2ma 0.2v ccq v v ih (2) input high voltage v ccq ? 0.4 v ccq + 0.2 v v il (3) input low voltage ?0.2 0.4 v i li input leakage current v in = 0 to v ccq 1a i lo output leakage current g = v ih or e = v ih 1a i cc1 (4) asynchronous read/write random at t rc min v in = 0v or v ccq , i out = 0ma, e = v il 25 ma i cc2 (4) burst, initial read/write access v in = 0v or v ccq i out = 0ma, e = v il 30 ma i cc3r (4) continuous burst read v in = 0v or v ccq i out = 0ma, e = v il 25 ma i cc3w (4) continuous burst write v in = 0v or v ccq i out = 0ma, e = v il 30 ma
m69km096aa dc and ac parameters 37/59 i pasr (4) partial array refresh standby current full array v in = 0v or v ccq e = v ccq 140 a 1/2 array 120 a 1/4 array 110 a 1/8 array 105 a none 95 a i sb (5) standby current v in = 0v or v ccq e = v ccq 140 a i ccpd deep-power down current v in = 0v or v ccq , v cc = v ccq = 1.95v, t a = +85c 310a 1. bcr5-bcr4 = 01 (default settings). 2. input signals may overshoot to v ccq + 1.0v for periods of less than 2ns during transitions. 3. output signals may undershoot to v ss ? 1.0v for periods of less than 2ns during transitions. 4. this parameter is specified with all outputs disabled to avoid external loading effects. the user must add the current required to drive output capacitance expected for the actual system. 5. i sb maximum value is measured at +85c with par set to full array. in order to achieve low standby current, all inputs must be driven either to v ccq or v ssq . i sb might be slightly higher for up to 500ms after power-up, or when entering standby mode. table 16. dc characteristics (continued) symbol parameter refreshed array test conditions min. typ max. unit
dc and ac parameters m69km096aa 38/59 figure 13. asynchronous random read ac waveforms ai11590 a16-a21 wait valid address tehqz tblqv hi-z tavax telqv tllqv tbhqz tghqz tglqv teltv valid output telqx tglqx e lb/ub g w adq0-adq15 tavqv hi-z tblqx l valid address tavlh tlhax tlllh tellh tehtz tlhqz tllqz
m69km096aa dc and ac parameters 39/59 figure 14. cr controlled configuration register read followed by read, asynchronous mode 1. a18-a19 must be set to ?00b? to select rcr, ?01b? to select the bcr, and ?1xb? to select the didr. a16, a17, a20, a21 address address a18-19 initiate configuration register access cr trhlh tlllh tehel telqv select configuration register l e g w ai11592 adq0-adq15 lb/ub tlhrl configuration register data valid data valid tavqv tllqv tehqz tglqx telqx address
dc and ac parameters m69km096aa 40/59 table 17. asynchronous read ac characteristics (1) symbol alt. parameter min max unit t avqv t aa address valid to output valid 70 ns t avax t rc read cycle time 70 ns t avlh t rhlh t avs address valid to l high configuration register high to l high 5ns t blqv t ba upper/lower byte enable low to output valid 70 ns t bhqz (2) t bhz upper/lower byte enable high to output hi-z 8 ns t blqx (3) t blz upper/lower byte enable low to output transition 10 ns t eltv t cew chip enable low to wait valid 1 7.5 ns t elqv t co chip enable low to output valid 70 ns t ellh t cvs chip enable low to l high 7 ns t ehel t cbph chip enable high between subsequent asynchronous operations 6ns t ehqz (2) t hz output enable high to output hi-z chip enable high to output hi-z 8ns t elqx (3) t lz chip enable low to output transition 10 ns t glqv t oe output enable low to output valid 20 ns t ghqz (2) t ohz output enable low to output hi-z 8 ns t glqx (3) t olz output enable low to output transition 3 ns t llqv t aadv latch enable low to output valid 70 ns t lhax t lhrl t avh latch enable high to address transition latch enable high to configuration register low 2ns t lhqz t ahz latch enable high output low-z 3 ns t llqz t ahz latch enable low output hi-z 8 ns t lllh t vp latch enable low pulse width 5 ns 1. these timings have been obtained in t he measurement conditions described in table 14: operating and ac measurement conditions and figure 12: ac measurement load circuit . 2. the hi-z timings measure a 100mv transition from either v oh or v ol to v ccq /2. 3. the low-z timings measure a 100m v transition from the hi-z (v ccq /2) level to either v oh or v ol .
m69km096aa dc and ac parameters 41/59 figure 15. asynchronous write ac waveforms 1. data inputs are hi-z if e is high, v ih . 2. when e is low, v il (device selected), w must not remain low, for longer than t eleh . 3. the end of the write operation is controlled by e , lb , ub , or w , whichever is de-asserted first. adq0-adq15 valid address hi-z hi-z tavax teltv valid input taveh, tavbh, tavwh telwh, teleh, telbh tdveh tblwh, tbleh, tblwh hi-z tehdx twlwh, twlbh, twleh (2) ai11593 a16-a21 wait lb/ub w l tavwl tehtz, tbhtz, twhtz valid address e tavlh tlhax tllwh, tlleh, tllbh tlllh
dc and ac parameters m69km096aa 42/59 figure 16. asynchronous write followed by read ac waveforms 1. when configured to operate in synchronous mode (bcr[15] = 0), e must remain high, v ih , for at least t eleh to schedule the appropriate refresh interval. otherwise, t eleh is only required after e controlled write operations. adq0- adq15 valid address hi-z tavax valid input tavwh telwh tdvwh tblwh hi-z twhdx twlwh ai12167 a16-a21 wait lb/ub w l tavwl valid address e tavlh tlhax tllwh valid address valid address valid output g tavlh tlhax tavqv tellh tehel (1) tehqz tbhqz tbhqz telqx tblqx tglqx tglqv tlllh tllqz tlhqz
m69km096aa dc and ac parameters 43/59 figure 17. cr controlled configuration register program, asynchronous mode 1. only the content of the bus configuration register (b cr) and refresh configuration register (rcr) can be modified. 2. the opcode is the value to be wr itten the configuration register. 3. cr is latched on the rising edge of l . there is no setup requirement of cr with respect to e . ai11597 a16, a17, a20, a21 opcode (2) l e g w a18-a19 00(rcr), 01(bcr) twlwh cr write add. value to configuration register trhlh tlhrl lb, ub first access to configuration register tlhax tavlh data valid address data valid address tehel telwh
dc and ac parameters m69km096aa 44/59 table 18. asynchronous write ac characteristics (1) symbol alt. parameter min max unit t avbl , t avel t avwl , t llwl t as address set-up to beginning of write operation 0 ns t avlh , t rhlh t avs address valid to latch enable high configuration register high to latch enable high 5ns t avwh , t aveh t avbh t aw address set-up to end of write operation 70 ns t avax t wc write cycle time 70 ns t blbh , t bleh t blwh t bw upper/lower byte enable low to end of write operation 70 ns t eltv t cew chip enable low to wait valid 1 7.5 ns t ehel t cbph chip enable high between subsequent asynchronous operations 6 ns t ellh t cvs chip enable low to l high 7 ns t elwh , t eleh t elbh t cw chip enable low to end of write operation 70 ns t ehdx t whdx t bhdx t dh input hold from write 0 ns t elwh , t dvbh t dveh , t dvwh t dw input valid to write setup time 20 ns t ehtz , t bhtz , t whtz (2) t hz chip enable high to wait hi-z lb /ub high to wait hi-z write enable high to wait hi-z 8ns t llwh , t lleh , t llbh t vs latch enable low to write enable high 70 ns t lhax , t lhrl t avh latch enable high to address transition or latch enable high to configuration register low 2ns t lllh t vp latch enable low pulse width 5 ns t whqz t ow end of write to input low-z 5 ns t wlbh , t wleh t wlwh (3) t wp write pulse width 45 ns t whwl t wph write enable pulse width high 10 ns 1. these timings have been obtained in the measurement conditi ons described in table 14: operating and ac measurement conditions and figure 12: ac measurement load circuit . 2. the hi-z timings measure a 100mv transition from either v oh or v ol to v ccq /2. the low-z timings measure a 100mv transition from the hi-z (v ccq /2) level to either v oh or v ol . 3. w low time must be limited to t ehel .
m69km096aa dc and ac parameters 45/59 figure 18. clock input ac waveform ai06981 tkhkh tf tr tkhkl tklkh table 19. clock related ac characteristics symbol alt. parameter m69km096aa unit 83mhz min max f clk f clk clock frequency 83 mhz t khkh t clk clock period 12 ns t khkl , t klkh t kp clock high to clock low, clock low to clock high 4 ns t r , t f t khkl clock rise time, clock fall time 1.8 ns
dc and ac parameters m69km096aa 46/59 figure 19. 4-word synchronous burst read ac waveforms (variable latency mode) 1. the latency is set to 3 cloc k cycles (bcr13-bcr11 = 101). the wait signal is active low (bcr10=0), and is asserted during delay (bcr8=0). a16-a21 wait adq0-adq15 k tavkh tkhkh tkhax tkhqv1 valid address tkhqx tehqz tkheh tllkh tglqx tehel telkh twhkh tkhwl tghqz tkhkl read burst identified tkhtx hi-z hi-z hi-z tglqv ai12100b e g w lb/ub (w = high) teltv tkhqv2 l tkhlh valid output valid output valid output valid output teleh tkhbh valid address tlhax
m69km096aa dc and ac parameters 47/59 figure 20. synchronous burst read suspend and resume ac waveforms 1. the latency type (bcr14) can be set to fixed or variable during burst read su spend operations.the latency is set to 3 clock cycles (bcr13-bcr11 = 101). the wait signal is active low (bcr 10=0), and is asserted during delay (bcr8=0). 2. during burst read suspend operations, the clock signal must be stopped (low). 3. g can be held low, v il , during burst suspend operations. if so, data output remain valid. don't care don't care a16-a21 wait adq0-adq15 k tavkh tkhax tkhqx tehqz tllkh tglqx tehel telkh twhkh tkhwl tblkh tghqz tavlh tkhkl hi-z valid output hi-z hi-z ai12101b e g w lb/ub tkhqv1 l valid output valid address valid address tglqv tghqz valid output valid output valid output valid output tkhlh tglqv tkhtx valid address tlhax tghav
dc and ac parameters m69km096aa 48/59 figure 21. burst read showing end-of-r ow condition ac waveforms (no wrap) 1. the wait signal is active low (bcr10=0) , and is asserted during delay (bcr8=0). a16-a21 adq0-adq15 k tkhtv tkhkh tklkh, tkhkl tf wait ai12102a e g lb/ub w don't care don't care l valid output valid output low low low high tehtz high-z end of row
m69km096aa dc and ac parameters 49/59 figure 22. cr controlled configuration register read followed by read, synchronous mode 1. a18-a19 must be set to ?00b? to select rcr, ?01b? to select the bcr, and ?1xb? to select the didr. address address data valid a16, a17, a20, a21 k tavkh l e w cr a18-a19 g adq0-adq15 ub, lb wait cr valid tkhrl ai12104b trhkh tllkh tkhlh telkh tehel tehqz tghqz teltv tglqx tkhqv2 high high-z tkhqx tkhax tkhqv1 tglqv tllkh tglqv add.valid tlhax tghav
dc and ac parameters m69km096aa 50/59 table 20. synchronous burst read ac characteristics (1) symbol alt. parameter m69km096aa unit 83mhz min max t avqv t aa address valid to output valid (fixed latency) 70 ns t avkh , t rhkh t qvkh , t llkh t blkh , t whkh t sp set-up time to active clock edge 3 ns t ehel (2) t cbph chip enable high between subsequent operations in full- synchronous or nor-flash mode. 6ns t eleh (2) t cem chip enable pulse width 4 s t eltv , t lltv t cew chip enable low to wait valid latch enable low to wait valid 17.5ns t elqv t co chip enable low to output valid 70 ns t elkh t csp chip enable low to clock high 4 ns t ehqz , t ehtz (3) t hz chip enable high to output hi-z or wait hi-z 8 ns t glqv t boe delay from output enable lo w to output valid in burst mode 20 ns t ghqz (3) t ohz output enable high to output hi-z 8 ns t glqx (4) t olz output enable low to output transition 3 ns t khqv1 t aba burst to read access ti me (variable latency) 46 ns t khqv2 t aclk clock high to output delay 9 ns t khax , t khbh t khwl , t kheh t khlh , t khqx t hd hold time from active clock edge 3 ns t llqv t aadv latch enable low to output valid (fixed latency) 70 ns t khtx , t khtv t khtl clock high to wait valid 9 ns t lhax t avh address hold from latch enable high (fixed latency) 2 ns t ghav t ohzs output enable high to address valid 8 ns 1. these timings have been obtained in the measurement conditions described in table 14: operating and ac measurement conditions and figure 12: ac measurement load circuit . 2. a refresh opportunity must be offered every t eleh . a refresh opportunity is possible either if e is high during the rising edge of k; or if e is high for longer than 15ns. 3. the hi-z timings measure a 100mv transition from either v oh or v ol to v ccq /2. 4. the low-z timings measure a 100m v transition from the hi-z (v ccq /2) level to either v oh or v ol .
m69km096aa dc and ac parameters 51/59 figure 23. 4-word synchronous burst write ac waveforms (variable latency mode) 1. the latency is set to 3 cloc k cycles (bcr13-bcr11 = 101). the wait sign al is active low (b cr10=0), and asserted during delay (bcr8=0). 2. the wait signal must remain assert ed for lc clock cycles (l c latency code), whatever the latency mode (fixed or variable). 3. t avll and t llwl , are required if t elkh > 20ns. a16-a21 wait adq0-adq15 k tkhkh valid address tkhdx telkh twlkh tkhwh tavkh write burst identified tkhtx hi-z valid input hi-z hi-z ai12105b e g w (w = low) tkheh tehel tblkh lb/ub teltv tdvkh l valid input valid input valid input teleh tkhax tavwl tllwl tllkh tkhlh high tehtz note 2 valid address
dc and ac parameters m69km096aa 52/59 figure 24. burst write showing end-of -row condition ac waveforms (no wrap) 1. the wait signal is active low (bcr10=0) , and is asserted during delay (bcr8=0). don't care a16-a21 adq0-adq15 k tkhkh tklkh tf wait ai12106a e g lb/ub w don't care l tkhdx tdvkh end of row high tkhtv tehtz high-z
m69km096aa dc and ac parameters 53/59 figure 25. synchronous burst write followed by read ac waveforms (4 words) 1. the latency type can set to fixed or variable mode. the latency is set to 3 cl ock cycles (bcr13-bcr11 = 101). the wait signal is active low (bcr10=0), and is asserted during delay (bcr8=0). 2. e can remain low between the burst read and burst write oper ation, but it must not be held low for longer than t eleh . a16-a21 wait adq0- adq15 k tkhax ai12107b e g w l tkhkh d in0 d in1 d in2 d in3 ub, lb tklkh tkhkl tavkh tkhlh tllkh telkh twlkh tkhwh tdvkh tehel tghqz tglqx tkhqx d o0 d o1 d o2 d o3 tkhdx tkhax tavkh (2) tkheh telkh tkhlh tkheh tkhtx tkhtx twhkh tkhwl valid add. valid add. valid add.
dc and ac parameters m69km096aa 54/59 figure 26. cr controlled configuration register program, synchronous mode 1. only the configuration register (bcr) and the re fresh configuration register (rcr) can be modified. 2. data inputs/outputs are not used. 3. the opcode is the value to be written in the configuration register. 4. a19 gives the configuration register address. 5. cr initiates the configuration register access. a16, a17, a20, a21 (3) k teleh hi-z ai11598 l e w cr (5) opcode a18-a19 (4) 00 (rcr) 01 (bcr) g ub, lb adq0-adq15 (2) wait tavkh tkhrl trhkh tllkh tkhlh tkhax twlkh tkhwh teltv
m69km096aa dc and ac parameters 55/59 table 21. synchronous burst write ac characteristics (1) symbol alt. parameter m69km096aa unit 83mhz min max t avwl t llwl (2) t as address set-up to beginning of write operation 0 ns t avkh t dvkh t wlkh t llkh t blkh t whkh t whwl t sp set-up time to active clock edge 3 ns t lhax t avh latch enable high to address transition (fixed latency) 2 ns t ehel (3) t cbph chip enable high between subsequent operations in full- synchronous or nor-flash mode. 6ns t eleh (3) t cem maximum chip enable low pulse 4 s t eltv t lltv t cew chip enable low to wait valid 1 7.5 ns t elkh t csp chip enable low to clock high 4 ns t ehdz t ehtz (4) t hz chip enable high to input hi-z or wait hi-z 8 ns t khax t khrl t khlh t khdx t kheh t khbh t khwh t hd hold time from active clock edge 3 ns t khtv tkhtx t khtl clock high to wait valid or low 9 ns 1. these timings have been obtained in t he measurement condi tions described in table 14: operating and ac measurement conditions and figure 12: ac measurement load circuit . 2. t avwl and t llwl , are required if t elkh > 20ns. 3. a refresh opportunity must be offered every t eleh . a refresh opportunity is possible either if e is high during the rising edge of k; or if e is high for longer than 15ns. 4. the hi-z timings measure a 100mv transition from either v oh or v ol to v ccq /2.
dc and ac parameters m69km096aa 56/59 figure 27. power-up ac waveforms 1. power must be applied to v cc prior to or at the same time as v ccq . figure 28. deep power-down entry and exit ac waveforms ai09465e v cc , v ccq tvchel 1.7v device ready for normal operation device initialization e ai11306b tehel(dp) device ready for normal operation e teleh (dp) deep power-down mode deep power-down entry (rcr4= 0) deep power-down exit tvchel device initialization table 22. power-up and deep power-down ac characteristics symbol alt. parameter min max unit t vchel t pu initialization delay after power-up or deep power-down exit 150 s t ehel(dp) t dpd deep power-down entry to deep power-down exit 10 s t eleh(dp) t dpdx chip enable low to deep power-down exit 10 s
m69km096aa part numbering 57/59 10 part numbering the notation used for the device number is as shown in ta bl e 2 3 . not all combinations are necessarily available. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest stmicroelectronics sales office. table 23. ordering information scheme example: m69km096aa c w 8 device type m69 = psram mode k = bare die operating voltage m= v cc = 1.7 to 1.95v, x16, multiplexed i/o, psram array organization 096 = 64 mbit (4 mbit x16) option 1 a = 1 chip enable silicon revision a = a die maximum clock frequency c = 83mhz package w = unsawn wafer operating temperature 8 = ?30 to 85 c
revision history m69km096aa 58/59 11 revision history table 24. document revision history date rev. revision details 15-dec-2005 0.1 first issue. 29-may-2006 1 80mhz clock frequency changed to 83mhz, and 104mhz removed. t ehel and t lhqz minimum values, and t llqz maximum value updated in table 17: asynchronous read ac characteristics . t ehel minimum values updated in table 18: asynchronous write ac characteristics . t lhax and t ghav added in table 20: synchronous burst read ac characteristics . t lhax added in figure 19 . t lhax and t ghav added in figure 20 and figure 22 . t khll removed from table 21: synchronous burst write ac characteristics , figure 23 and figure 25 . t pu changed to t vchel in table 22: power-up and deep power-down ac characteristics , figure 27 and figure 28 . wafer and die specifications section removed. maximum clock frequency identifier changed from ?80? to ?c? in ta bl e 2 3 : ordering information scheme . 6-jul-2006 2 updated section 6.3.3: row boundary crossing on page 18 , figure 21: burst read showing end-of-row condition ac waveforms (no wrap) on page 48 , figure 23: 4-word synchronous burst write ac waveforms (variable latency mode) on page 51 , figure 24: burst write showing end-of-row condition ac waveforms (no wrap) on page 52 , hold time from active clock edge value in table 20: synchronous burst read ac characteristics and ta b l e 2 1 : synchronous burst write ac characteristics .
m69km096aa 59/59 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of M69KM096AACW8

	To Download M69KM096AACW8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .